Non-volatile semiconductor memory arrays with memory cells having charge storage capability are well known in the art. Examples of such memory arrays are described in the cross-referenced application entitled METHOD AND APPARATUS TRANSPORTING CHARGES IN SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MEMORY DEVICE.
In non-volatile memories, a typical bit line can be a number of millimeters long. The long bit line results in a large resistance if the bit line junction is not heavily doped and deep. With a large resistance, a large voltage drop occurs along the bit line in the presence of significant bit line current. Although a heavily doped and deep bit line junction can reduce the resistance, such a heavily doped and deep bit line junction causes serious short channel effects to the memory cell. There is a problem with and a trade-off between the bit line resistance and the short channel effects in non-volatile memories. To prevent the short channel effects for a gate length of 45 nanometers or below, the bit line junction is required to be as shallow as 20 nanometers and the doping level in the bit line junction is required not to exceed 5×1019 atoms/cm3. However, such shallow and lightly doped junction results in a sheet resistance of 1000 Ohms/square or higher.
In light of the above background, there is a need for improved memory cells, improved arrays and improved steps for arranging memory cells and arrays.
Other objects and further understanding of the objects will be realized by referencing to the specification and drawings.